The present invention relates generally to the field of integrated circuits and, in particular, to radiation protection of integrated circuits.
Using integrated circuits in space-related applications requires protecting these circuits from space radiation, such as solar flares, galactic and cosmic radiation, Van Allen trapped electron and proton belts, and neutron and gamma radiation. One method commonly used for protecting circuits from space radiation involves building radiation protection into the chip design. This method involves modifying specific front-end designs and processes to provide radiation protection at the device level. This method is expensive and may delay the release products date, thus the resulting radiation-protected circuits are typically at least two generations behind state-of-the-art technology of non-protected circuits.
Another method commonly used for protecting circuits from space radiation involves testing each part or die lot to obtain the necessary level of radiation protection. This results in significant expenses because of the large amount of required testing. Significant cost is also incurred, because roughly only ten percent of the tested products can be used.
Shielding is yet another method for guarding integrated circuits against space radiation. The shielding technique may include shielding an entire satellite or subsystem. Unfortunately, the materials used to provide this protection add significant weight and cost to the design. Shielding may also include shielding individual integrated circuits, which is cost prohibitive because a custom package would have to be manufactured for each circuit configuration. This method is weight, size, and cost prohibitive.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for cost-effective, weight- and size-conserving techniques that do not cause product-release date delays and that provide total radiation protection for integrated circuits used in space-related applications.
The above-mentioned problems with weight, size, cost, product-release date delays, and total radiation protection and other problems related to protecting integrated circuits used in space-related applications from electromagnetic radiation are addressed by embodiments of the present invention and will be understood by reading and studying the following specification.
One embodiment of the present invention provides a method for manufacturing a microchip. The method includes forming a plurality of alternating metallic wiring-layers and non-metallic layers on a wafer, terminating with a metallic wiring-layer. The method includes forming a plurality of vias for electrically interconnecting various metallic wiring-layers and forming a plurality of electrically conducting pads adjacent various vias. Forming a passivation layer adjacent the terminal metallic wiring-layer and the plurality of conducting pads and removing a portion of the passivation layer to expose the plurality of conducting pads are also included in the method. The method includes forming a layer adjacent the passivation layer and the plurality of exposed conducting pads for protecting the microchip against electromagnetic radiation. The method includes removing a portion of the protective layer to expose the plurality of conducting pads. Isolating each conducting pad, electrically, from the protective layer and forming an electrically conducting bump on each conducting pad are also included in the method.